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authorGuillaume Seguin <guillaume@segu.in>2009-01-10 01:49:49 +0100
committerGuillaume Seguin <guillaume@segu.in>2009-01-10 01:49:49 +0100
commit2f8d9dd471b38e585955a6d5b040e4664af03503 (patch)
tree16b197c556f69810e894330a35771580ca0d9e84
parentaf732e1a70a6333cf74250846f7ebaf9127477ce (diff)
downloadsysdigit-2f8d9dd471b38e585955a6d5b040e4664af03503.tar.gz
sysdigit-2f8d9dd471b38e585955a6d5b040e4664af03503.tar.bz2
[circuitframework] Add BusIn/Out components handling
-rw-r--r--logiccircuitframework/components.py28
1 files changed, 27 insertions, 1 deletions
diff --git a/logiccircuitframework/components.py b/logiccircuitframework/components.py
index 60315b0..9f6cbcd 100644
--- a/logiccircuitframework/components.py
+++ b/logiccircuitframework/components.py
@@ -159,6 +159,32 @@ class Xor(Component):
symbol = "^"
+class BusIn(Component):
+
+ symbol = "BI"
+ outputs = 1
+
+class BusOut8(Component):
+
+ symbol = "BO8"
+ fixed_inputs = True
+ inputs = 1
+ outputs = 8
+
+class BusOut16(Component):
+
+ symbol = "BO16"
+ fixed_inputs = True
+ inputs = 1
+ outputs = 16
+
+class BusOut32(Component):
+
+ symbol = "BO32"
+ fixed_inputs = True
+ inputs = 1
+ outputs = 32
+
class Input(Component):
symbol = "i"
@@ -292,7 +318,7 @@ class ROMR(Component):
DEFAULT_COMPONENT_TYPES = [Not, And, Or, Nand, Nor, Xor, Input, Output,
Reg, RegInput, RegOutput, Mux, One, Zero,
- RAMR, RAMW, ROMR]
+ RAMR, RAMW, ROMR, BusIn, BusOut8, BusOut16, BusOut32]
class ComponentsPool(object):